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Silicon Labs /MGM240PB32VNN /CMU_S /WDOG0CLKCTRL

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Interpret as WDOG0CLKCTRL

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https://regviz.com/r/Silicon Labs/EFR32BG22C224F512GM32/CMU_S/WDOG0CLKCTRL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLKSEL

Description

No Description

Fields

CLKSEL

Clock Select

1 (LFRCO): LFRCO is clocking WDOG0CLK

2 (LFXO): LFXO is clocking WDOG0CLK

3 (ULFRCO): ULFRCO is clocking WDOG0CLK

4 (HCLKDIV1024): HCLKDIV1024 is clocking WDOG0CLK

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data